1. Field of the Invention
The present invention relates to a packaging chip formed in a multi-layer structure of stacking plural wafers in serial order and a fabrication method therefor and, more particularly, to a packaging chip having interconnection electrodes directly connecting each wafer from a uppermost wafer and a fabrication method therefor.
2. Description of the Related Art
The electronic chip diversely used in various electronic products can be easily damaged by external shocks since the electronic chip has a minute electronic circuit therein. Thus, a packaging process is inevitably required in chip fabrication processes.
The packaging process refers to a task of forming a physical function and a shape in order for a circuit device to be mounted. That is, the packaging process refers to a task of hermetically sealing a circuit device in order to prevent introduction of foreign material into the circuit device or prevent the circuit device from being damaged by external shocks. For hermetical sealing of the circuit device, a separate substrate is used for a packaging substrate to be formed, and the packaging substrate is bonded to a base substrate in which the circuit device is mounted. As above, a packaging-processed chip is generally referred to as a packaging chip.
In particular, the wafer level packaging is processed to meet the trend of recent electronic products such as compactness, high-performance, and so on. Further, for high-performance, plural wafers are stacked in a multi-layer structure so that circuit devices of diverse kinds can be mounted in the individual layers. In here, each wafer plays a role of packaging a circuit device mounted on a wafer located below itself. The packaging chip structured as above is generally referred to as a 3D packaging chip. Meanwhile, since the 3D-structured packaging chip uses plural wafers, plural interconnection electrodes are needed. Each interconnection electrode supplies external electric power to circuit wirings on each wafer stacked in serial order.
Conventionally, for the formation of the 3D-structured packaging chip, an interconnection electrode is formed to connect lower and upper wafers every time a wafer is stacked. That is, the second wafer is bonded over the first base wafer, and an interconnection electrode is formed to pass through the second wafer so that the upper surface of the second wafer is electrically connected to the base wafer. Next, the third wafer is bonded, and an interconnection electrode is formed to pass through the third wafer. Here, for connections to the base wafer, a structure is required which connects the interconnection electrode on the second wafer and the interconnection electrode on the third wafer. In general, ball bumps are used to connect the interconnection electrodes one another.
However, such a conventional packaging chip fabrication process requires a via-forming process for forming interconnection electrodes every time each wafer is stacked. Thus, the via-forming process is performed several times, during which the wafers can be damaged. As a result, there exists a problem of deteriorating fabrication yield.
Further, in the conventional packaging chip, an interconnection electrode is separately formed on each wafer and connected by means of the ball bump or the like. That is, the interconnection electrode is not directly connected to each wafer, but connected indirectly by means of the ball bump or the other interconnection electrode. Thus, the thermal expansion or contraction of the interconnection electrode can break the electrical connections of the interconnection electrode to the ball bump. Accordingly, there exists a problem of degrading reliability and performance of a packaging chip.
Further, a signal can be leaked out due to a high-resistance value of the ball bump connecting each interconnection electrode. Thus, there exists a problem of degrading the entire performance of the packaging chip.
Further, in a process of arranging and bonding each wafer in order, the arrangement mismatch can occur due to the ball bumps. That is, if plural ball bumps are formed on one wafer, the wafers may not be precisely arranged in order due to height differences, areas, and so on. If a multi-layer structure is formed in such circumstances, there can occur a problem of degrading the performance of the packaging chip due to accumulation of the arrangement errors.